1. Field of the Invention
The present invention relates to a switching DC-to-DC converter and, More particularly, to a switching DC-to-DC converter provided with multiple power supply channels for supplying multiple output voltages, capable of improving transient noise caused by power switch transistors, in which the multiple power supply channels may all adopt voltage mode feedback control, or some of them adopt voltage mode feedback control and others adopt current mode feedback control.
2. Description of the Related Art
Typically, a switching DC-to-DC converter regulates a DC voltage source for supplying a DC output voltage with a desired voltage level by appropriately controlling a duty cycle of a power switch transistor. Where the DC output voltage is larger than the DC voltage source, the switching DC-to-DC converter is generally referred to as a boost converter or regulator. On the other hand, the switching DC-to-DC converter is generally referred to as a buck converter or regulator where the DC output voltage is smaller than the DC voltage source. In order to ensure the stability of the DC output voltage, the switching DC-to-DC converter is usually provided with a feedback circuit, which may be classified as either a voltage mode feedback or a current mode feedback. In regarding to the voltage mode feedback, the feedback circuit retrieves a certain ratio of the DC output voltage for generating a feedback signal. In regarding to the current mode feedback, the feedback circuit generates a feedback signal by using a current sense amplifier to detect an inductor current. Also, the current mode feedback circuit may further retrieve a certain ratio of the DC output voltage in order to perform slope compensation.
Many of today's electronic system products effectively perform systematic operations and provide desired results by combining a variety of functional modules. For example, a digital camera is made up of a liquid crystal display, a backlight module, an image sensor, a digital signal processor, and a memory, thereby achieving the display, capture, and storage of digital images. In this case, each of the liquid crystal display, backlight module, image sensor, digital signal processor, and memory needs a DC power supply for executing the respectively designated operation and function. Typically, the functional modules incorporated in one electronic system product adopt different DC power supplies, respectively. That is, they are designed to operate with different DC power supply voltages. Since the electronic system product usually has only one DC voltage source such as a battery, a plurality of switching DC-to-DC converters are necessary to provide a plurality of different DC output voltages. As a conventional practice, the plurality of switching DC-to-DC converters are integrally manufactured in a single semiconductor integrated circuit chip for avoiding unnecessary packaging and wiring processes, thereby achieving advantages of low cost and small size as well as reducing parasitic capacitances and inductances. In this case, the plurality of switching DC-to-DC converters are formed as multiple power supply channels of the single semiconductor integrated circuit chip, which are connected in parallel between a common DC voltage source and ground and have respective output terminals for providing a plurality of different DC output voltages.
FIG. 1(a) is a circuit block diagram showing a conventional switching DC-to-DC converter 10 with multiple output voltages. Referring to FIG. 1(a), the switching DC-to-DC converter 10 has four power supply channels 11A to 11D for converting a single DC voltage source Vsource, shown in FIG. 1(b), into four DC output voltages Vout1 to Vout4, respectively. The power supply channel 11A includes a switching controller 12A, a converting circuit 13A provided with a power switch transistor 15A, and a feedback circuit 14A. The power switch transistor 15A is driven by a pulse-width-modulated (PWM) control signal PWM1 output from the switching controller 12A. The PWM control signal PWM1 uses its duty cycle to determine the voltage level converting relationship between the DC voltage source Vsource and the DC output voltage Vout1. In other words, under a condition that the DC voltage source Vsource is fixed, the voltage level of the DC output voltage Vout1 can be manipulated by appropriately adjusting the duty cycle of the PWM control signal PWM1. In additional, the switching controller 12A adjusts the duty cycle of the PWM control signal PWM1 after receiving a feedback signal FB1 generated by the feedback circuit 14A in order to maintain the DC output voltage Vout1 stable.
The power supply channel 11B includes a switching controller 12B, a converting circuit 13B provided with a power switch transistor 15B, and a feedback circuit 14B. The power switch transistor 15B is driven by a PWM control signal PWM2 output from the switching controller 12B. The PWM control signal PWM2 uses its duty cycle to determine the voltage level converting relationship between the DC voltage source Vsource and the DC output voltage Vout2. The switching controller 12B adjusts the duty cycle of the PWM control signal PWM2 after receiving a feedback signal FB2 generated by the feedback circuit 14B in order to maintain the DC output voltage Vout2 stable. The power supply channel 11C includes a switching controller 12C, a converting circuit 13C provided with a power switch transistor 15C, and a feedback circuit 14C. The power switch transistor 15C is driven by a PWM control signal PWM3 output from the switching controller 12C. The PWM control signal PWM3 uses its duty cycle to determine the voltage level converting relationship between the DC voltage source Vsource and the DC output voltage Vout3. The switching controller 12C adjusts the duty cycle of the PWM control signal PWM3 after receiving a feedback signal FB3 generated by the feedback circuit 14C in order to maintain the DC output voltage Vout3 stable. The power supply channel 11D includes a switching controller 12D, a converting circuit 13D provided with a power switch transistor 15D, and a feedback circuit 14D. The power switch transistor 15D. is driven by a PWM control signal PWM4 output from the switching controller 12D. The PWM control signal PWM4 uses its duty cycle to determine the voltage level converting relationship between the DC voltage source Vsource and the DC output voltage Vout4. The switching controller 12D adjusts the duty cycle of the PWM control signal PWM4 after receiving a feedback signal FB4 generated by the feedback circuit 14D in order to maintain the DC output voltage Vout4 stable.
An oscillator 16 outputs a pulse signal PULSE1 and a ramp signal RAMP1 to the switching controller 12A. Rising edges of the pulse signal PULSE1 occur simultaneously with falling edges of the ramp signal RAMP1. The pulse signal PULSE1 sets the switching controller 12A to generate the rising edge of the PWM control signal PWM1, which is then used for turning on the power switch transistor 15A. The ramp signal RAMP1 and the feedback signal FB1 determine the occurrence of the falling edge of the PWM control signal PWM1, which is then used for turning off the power switch transistor 15A. The oscillator 16 further outputs a pulse signal PULSE2 and a ramp signal RAMP2 to the switching controller 12B. Rising edges of the pulse signal PULSE2 occur simultaneously with falling edges of the ramp signal RAMP2. The pulse signal PULSE2 sets the switching controller 12B to generate the rising edge of the PWM control signal PWM2, which is then used for turning on the power switch transistor 15B. The ramp signal RAMP2 and the feedback signal FB2 determine the occurrence of the falling edge of the PWM control signal PWM2, which is then used for turning off the power switch transistor 15B. The oscillator 16 still further outputs a pulse signal PULSE3 and a ramp signal RAMP3 to the switching controller 12C. Rising edges of the pulse signal PULSE3 occur simultaneously with falling edges of the ramp signal RAMP3. The pulse signal PULSE3 sets the switching controller 12C to generate the rising edge of the PWM control signal PWM3, which is then used for turning on the power switch transistor 15C. The ramp signal RAMP3 and the feedback signal FB3 determine the occurrence of the falling edge of the PWM control signal PWM3, which is then used for turning off the power switch transistor 15C. The oscillator 16 still further outputs a pulse signal PULSE4 and a ramp signal RAMP4 to the switching controller 12D. Rising edges of the pulse signal PULSE4 occur simultaneously with falling edges of the ramp signal RAMP4. The pulse signal PULSE4 sets the switching controller 12D to generate the rising edge of the PWM control signal PWM4, which is then used for turning on the power switch transistor 15D. The ramp signal RAMP4 and the feedback signal FB4 determine the occurrence of the falling edge of the PWM control signal PWM4, which is then used for turning off the power switch transistor 15D.
Referring to FIG. 1(b), the power supply channels 11A to 11D are connected in parallel between the DC voltage source Vsource and ground. More specifically, through bonding wires, the power supply channels 11A to 11D are connected in parallel between the DC voltage source Vsouce and ground. As a result, a plurality of parasitic inductances Lw caused by the bonding wires exist between the DC voltage source Vsource and the power supply channels 11A to 11D. Similarly, a plurality of parasitic inductances Lw caused by the bonding wires exist between the power supply channels 11A to 11D and ground. In the operation of the power supply channels 11A to 11D, the power switch transistors 15A to 15D of the converting circuits 13A to 13D are so periodically switched as to achieve the voltage converting functions. Due to the existence of the parasitic inductances Lw, noise is caused by a transient spike generated each time when any of the power switch transistors 15A to 15D makes a switching transition.
FIG. 1(c) is a waveform timing chart showing the pulse signals PULSE1 to PULSE4 and the ramp signals RAMP1 to RAMP4 generated by the conventional oscillator 16. As shown in FIG. 1(c), the pulse signals PULSE1 to PULSE4 are identical in waveform and in phase while the ramp signals RAMP1 to RAMP4 are identical in waveform and in phase. For this reason, what the oscillator 16 actually does is to generate a single pulse signal and a single ramp signal for simultaneously supplying to the switching controllers 12A to 12D of the power supply channels 11A to 11D. In the prior art, the oscillator 16 may have a simpler configuration with benefits of small size and low cost. However, the in-phase pulse signals PULSE1 to PULSE4 set the switching controllers 12A to 12D such simultaneously that the power switch transistors 15A to 15B then make switching transitions at the same time. As a result, the transient spikes caused by all of the power switch transistors 15A to 15B superpose together. Therefore, there is significantly large transient noise between the DC voltage source Vsource and ground, deteriorating qualities of the DC outsource put voltages Vout1 to Vout4 and much likely damaging the power supply channels 11A to 11D.